A 5 GHz Ring-Oscillator PLL with Active Delay-Discriminator Phase Noise Cancellation Loop by

i ABSTRACT Voltage Control Oscillator (VCO) is one of the most critical blocks in Phase Lock Loops (PLLs). LC-tank VCOs have a superior phase noise performance, however they require bulky passive resonators and often calibration architectures to overcome their limited tuning range. Ring oscillator (RO) based VCOs are attractive for digital technology applications owing to their ease of integration, small die area and scalability in deep submicron processes. However, due to their supply sensitivity and poor phase noise performance, they have limited use in applications demanding low phase noise floor, such as wireless or optical transceivers. Particularly, out-of-band phase noise of RO-based PLLs is dominated by RO performance, which cannot be suppressed by the loop gain, impairing RF receiver's sensitivity or BER of optical clock-data recovery circuits. Wide loop bandwidth PLLs can overcome RO noise penalty, however, they suffer from increased in-band noise due to reference clock, phase-detector and charge-pump. The RO phase noise is determined by the noise coming from active devices, supply, ground and substrate. The authors adopt an auxiliary circuit with inverse delay sensitivity to supply noise, which compensates for the delay variation of inverter cells. Feed-forward noise-cancelling architecture that improves phase noise characteristic of RO based PLLs is presented. The proposed circuit dynamically attenuates RO phase noise contribution outside the PLL bandwidth, or in a preferred band. The implemented noise-cancelling loop potentially enables application of RO based ii PLL for demanding frequency synthesizers applications, such as optical links or high-speed serial I/Os. The PLL is fabricated in a 90 nm CMOS technology. The core of the IC occupies 0.38mm × 0.32mm silicon area. The current consumption of the PLL is 24.7 mA when the cancellation technique enabled. PLL output spectra at 5.1 GHz when the PLL divider is modulated with a 10 MHz clock signal. Phase noise reduces in the cancellation bandwidth up to 20 MHz with a 200 kHz PLL loop bandwidth. The proposed cancellation loop suppresses the phase noise at 1 MHz offset by 12.5 dB and reference spur by 13dB, with a quiescent power consumption of 3.7 mA. iii ACKNOWLEDGEMENTS